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STK12C68-L25 Datasheet

Parameter Symbol Values Unit
Collector-emitter voltage VCE 1 200 V
Collector-gate voltage RGE = 20 kl VCGR 1 200
Gate-emitter voltage E ±20
DC collector current TC = 25 aC TC = 80 aC C 21 0 1 50 A
Pulsed collector current, tp = 1 ms TC = 25 aC TC = 80 aC /Cpuls 420 300
Power dissipation per IGBT TC = 25 aC Ptot 1 250 W
Chip temperature Ti +150 aC
Storage temperature Tstq -40+125


STK12C68-L25 Price

BAi BAo Aii Aio A9 A8 A7 A6 As A4 A3 A2 Ai Ao Address Bu
J J J J J J J J
RFU O RFU DLL T CAS Latency BT Burst Length Mode Regist
rJ
} 'stMode } DLL Test J Burst Type
A8 DLL Reset A7 mode A3 Type
0 No O Normal 0 Sequential
1 Yes 1 Test 1 Interleave
Burst Length
CAS Latency A2 A1 Ao Burst Type
BAo AnAo A6 As A4 Latency Sequential Interleave
0 MRS 0 0 0 Reserved O 0 0 Reserve Reserve
1 EMRS 0 O 1 Reserved O 0 1 2 2
0 1 0 Reserved O 1 0 4 4
0 1 1 3 0 1 1 8 8
* RFU(Reserved for future use) 1 O 0 Reserved 1 0 0 Reserve Reserve
should stay "0" during MRS cycle. 1 O 1 Reserved 1 0 1 Reserve Reserve
1 1 0 Reserved 1 1 0 Reserve Reserve
1 1 1 Reserved 1 1 1 Reserve Reserve


STK12C68-L25 on stock

1 339 0 968
(34.01) (24.58) - i- PIN l INDICATOR 0.147 (3 t3)
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knowledged. The in-service bit of a particular chan- nel may be cleared by writing a zero to the corre- sponding bit in ISRA or ISRB. Typically, this will be done at the conclusion of the interrupt routine just before the return. Thus no lower prionty channel will be allowed to request service until the higher priority channel is complete, while channels of still higher priority will be allowed to request service. While the in-service bit is set, a second interrupt on that chan- nel may be received and latched into the pending bit, though no service request will be madein re- sponse to the second interrupt until the in-service bit is cleared. ISRA and ISRB may be read at any time. Only a zero may be written into any bit of ISRA and ISRB ; thus the in-service bits may be cleared in soft- ware but cannot be set in software. This allows any one bit to be cleared, without altenng any other bits, simply by writing all ones except for the bit position to be cleared to ISRA or ISRB, as with IPRA and