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STK22C48-WF25 Datasheet

(4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchas- ing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements.
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AD7893-8051 Interface Figure 6 shows an interface between the AD7893 and the 8XC51 microcontroller. The 8XC51 is configured for its Mode 0 serialinterface mode. The diagram shows the simplest form of the interface where the AD7893 is the only part connected to the serial port of the 8XC51 and, therefore, no decoding of the serial read operations is required. It also makes no provisions for monitoring when conversion is complete on the AD7893.
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SYMBOL	PARAMETER	CONDITION	MINIMUM	MAXIMUM	UNIT
VIH	High-level input voltage	(TTL)	2.4		V
VIL	Low-level input voltage	(TTL)		0.8	V
VOL1	Low-level output voltage	10L = 4.OmA, VDD = 4.5V (TTL)		0.4	V
VOL2	Low-level output voltage	IOL = 200ptA, VDD = 4.5V (CMOS)		VSS+ 0.10	V
VOH1	High-level output voltage	IOH = -200ptA, VDD = 4.5V (CMOS)	VDD -0.1		V
VOH2	High-level output voltage	IOH = -2.OmA, V DD = 4.5V (TTL)	2.4		V
CIN 1	Input capacitance	f = 1MHz, VDD = 5.OV VIN = OV		15	pF
CI0 1,4	Bidirectional I/O capacitance	f = 1MHz, VDD = 5.OV VOUT = OV		15	pF
IIN	Input leakage current	VIN = OV to VDD	-5	5
IOZ	Three-state output leakage current	VO = OV to VDD VDD = 5.5V OE= 5.5V	-10	10
IOS 2,3	Short-circuit output current	VDD = 5.5V, VO = VDD VDD = 5.5V, VO = OV	-90	90	mA mA
lDDl(OP)J	Supply current operating @25.OMHz (40ns product) @22.2MHz (45ns product)	TTL inputs levels (IOUT = O), VIL = 0.2V _ VDD, PE = 5.5V		125 117	mA mA
IDD2(SB) post-rad	Supply current standby	CMOS input levels VIL = VSS +0.25V CE = VDD - 0.25 VIH = VDD - 0.25V		2	mA

For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is recommended (see Figure 6 0n page 6 and Figure 7 0n page 7). Ci and C2 are used to match the loop antenna to the power amplifier where Ci typically is 3.9 pF/NPO and C2 iS l pF/NPO; for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the ZLoad,opt by using standard valued capacitors.

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