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STK402-100S TW Datasheet

Pin Name	Function
SEGO to SEG63	Outputs to segment pins of LCD. Output level changes at each latch pulse LP falling edge.
XSCL	Data shift clock input: display data is shifted in on the falling edge of this signal.
LP	Latch pulse for displayed data, falling edge trigger: display data is latched on the falling edge of this signal.
FR	LCD AC-drive signal
El	Active high daisy chain enable input
EO	Active high daisy chain enable output
ECL	Daisy chain enable clock: the daisy chain enable is propagated on the falling edge of this clock.
DO to D3	4-bit display data input
TEST	Test output
VDD, Vss	Logic power inputs
v2, V3, VSSH	LCD drive power inputs VSSH: -14V to -23V VDD > V2 > V3 > VSSH

STK402-100S TW Price

Neither CISSOID, nor any of its directors, employees or affiliates make any representations or extend any warranties of any kind, either express or implied, including but not limited to warranties of merchantability, fitness for a particular purpose, and the absence of latent or other defects, whether or not discoverable. In no event shaH CISSOID, its directors, employees and affiliates be liable for direct, indirect, special, incidental or consequential damages of any kind arising out of the use of its circuits and their documentation, even if they have been advised of the possibility of such a damage. The circuits are provided "as is". CISSOID has no obligation to provide maintenance, support, updates, or modifications.
STK402-100S TW on stock

NOTES: 1. CPD iS used to determine the dynamic power dissipation (PD in yW) PD = CPD X VCC2 x fi + E (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; Vcc = supply voltage in V; E (CL x VCC2 x fo) = sum of outputs.

Z	J- OPEN z o- 4hiFi	5 Sl-3000C 2 4 1	Lo	2 47yF
Z				2 47yF

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