STK402-930 P-B Datasheet| Pin No. | Synbol | I/O | unctions | | LC7940YD | LC7941YD | | 91 | 90 | VDD | | | | 86 | 95 | VsS | Supply | VDD - VSS iS the logic supply. VDD -VEE iS the LCD supply. | | 87 | 94 | VEE | | 92 | 89 | V1 | | LCD panel drive voltage supplies | | 89 | 92 | V3 | Supply | Vi and VEE are selected levels. | | 88 | 93 | V4 | V3 and V4 are not-selected levels. | | 100 | 81 | CP | l | Display data Input clock (falling-edge trigger). | | 99 | 82 | CDI | l | Chip disable. Data is read in when LOW, and not road in when HIGH. | | 98 | 83 | LOAD | I | Display data latch clock (falling-edge trigger). On the falling edge, the LCD drive signals set by the display data are output. | | 97 | 84 | SDI | l | Serial data input. | | | | | |
STK402-930 P-B Price| Hitachi Code | MPAK-5 | | lJEDEC | | | lEIAJ | | | Weight (reference value) | 0.015 a | | |
STK402-930 P-B on stock| | | TA= -40IC | TA= OIC | TA= +25IC | TA= +85IC | | | Symbol | Parameter | Min | Typ. | Max | Min | Typ. | Max | Min | Typ. | Max | Min | Typ. | Max | Unit | | VOL | Output LOW Voltage(2,3) (QR, QR) | 3.05 | 3.23 | 3.35 | 3.05 | 3.24 | 3.37 | 3.05 | 3.24 | 3.37 | 3.05 | 3.25 | 3.41 | V | | VOH | Output HIGH Voltage(2,3) (QR, QR) | 3.92 | 4.05 | 4.11 | 3.98 | 4.09 | 4.16 | 4.02 | 4.11 | 4.19 | 4.09 | 4.16 | 4.28 | V | | VOL | Output LOW Voltage(2,4) (QT, QT) | 1.94 | 2.22 | 2.50 | 1.83 | 2.12 | 2.41 | 1.80 | 2.10 | 2.39 | 1.77 | 2.06 | 2.35 | V | | VOH | Output HIGH Voltage(2,4) (QT, QT) | 3.71 | 3.89 | 4.08 | 3.79 | 3.98 | 4.17 | 3.83 | 4.02 | 4.20 | 3.90 | 4.09 | 4.28 | V | | lcc | Quiescent Supply Current(5) | 20 | 25 | 42 | 22 | 26 | 47 | 23 | 27 | 47 | 25 | 28 | 47 | mA | | VIL | Input LOW Voltage(2) (DR,DR & DT,DT) | 3.05 | | 3.50 | 3.05 | | 3.52 | 3.05 | | 3.52 | 3.05 | | 3.56 | V | | VIH | Input HIGH Voltage(2) (DR,DR & DT,DT) | 3.77 | | 4.11 | 3.83 | | 4.16 | 3.87 | | 4.19 | 3.94 | | 4.28 | V | | IlL | Input LOW Current (DR,DR & DT,DT) | | | 150 | | | 150 | | | 150 | | | 150 | | | IIH | Input HIGH Current (DR,DR & DT,DT) | 0.5 | | | 0.5 | | | 0.5 | | | 0.5 | | | | | VIL | Input LOW Voltage SEL | | | 0.8 | | | 0.8 | | | 0.8 | | | 0.8 | V | | VIH | Input HIGH Voltage SEL | 2.0 | | | 2.0 | | | 2.0 | | | 2.0 | | | V | | I|L | Input LOW Current SEL VIN = 500mV | | | 600 | | | 600 | | | 600 | | | 600 | | | IIH | Input HIGH Current SEL VIN = 2.7V VIN = Vcc | | | 20 100 | | | 20 100 | | | 20 100 | | | 20 100 | | | VBB | Output Reference Voltage(2) | 3.57 | 3.63 | 3.70 | 3.62 | 3.67 | 3.73 | 3.65 | 3.70 | 3.75 | 3.69 | 3.75 | 3.81 | V | | | | | | | | | | | | | | | |
Ti = TA + (PD x OIA ) The power dissipated in the package (PD) iS the sum of the quies- cent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (Vs) times the quiescent current (Is). Assuming the load (RL) is referenced to midsupply, then the total drive power is Vs /2 X IOUT, some of which is dissipated in the package and some in the load (VOUT X IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package.
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