Notes: 14. The clocks (RCLK, WCLK) can be free-running during reset._ 15. After reset, the outputs will be LOW if OE = O and three-state if OE=1. 16. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers.
Si9730ABY-T1-E3 Price| |
| Ordercode | Input voltage ra nge | Output 1 | Output 2 | Rpple and noise max. |
| TYL05-05S30 TYL05-12S12 TYL05-15S10 TYL05-05W08 TYL05-12W06 TYL05-15W05 | 4.75 -6 VDC | 5 VDC/ 300 mA 12 VDC/ 120 mA 15 VDC/ 100 mA +5 VDC/ 80 mA +12 VDC/ 65 mA +15 VDC/ 53 mA | -5 VDC/ 80 mA -12 VDC/ 65 mA -15 VDC/ 53 mA | 6 mVpk-pk 6 mVpk-pk 6 mVpk-pk 6 mVpk-pk 6 mVpk-pk 6 mVpk-pk |
| 1VL05-1220 1VL05-1225 1VL05-1516 1VL05-1520 | 4.75 -6 VDC | +12 VDC/ 200 mA +12 VDC/ 250 mA +15 VDC/ 165 mA +15 VDC/ 200 mA | -12 VDC/ 200 mA -12 VDC/ 125 mA -15 VDC/ 165 mA -15 VDC/ 100 mA | 3 mVpk-pk 3 mVpk-pk 3 mVpk-pk 3 mVpk-pk |
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Si9730ABY-T1-E3 on stock
