| Part | Type differentiation | Marking | Package |
| RS07B | Single Diodes | RB | SMF |
| RS07D | Single Diodes | RD | SMF |
| RS07G | Single Diodes | RG | SMF |
| RS07J | Single Diodes | RJ | SMF |
| | | |
The parity error, framing error, and overrun error (if any) are strobed into the SR at the received character boundary before the RxRDY status bit is set. If a break condition is detected (RxD is Low for the entire character including the stop bit), a character consisting of all zeros will be loaded into the RHR and the received break bit in the SR is set t0 1. The RxD input must return to high for two (2) clock edges of the Xl crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. This will usually require a high time of one Xl clock period or 3 X1 edges since the clock of the controller is not synchronous to the Xl clock.
