| DO-D7 CSN R/WN A1-A4 RESETN DTACKN INTRN IACKN X1/CLK X2 RxDA RxDB TxDA TxDB OPO OP1 OP2 OP3 OP4 OP5 OP6 OP7 IPO IP1 IP2 IP3 IP4 IP5 Vcc GND | I/O I I I I 0 0 I I I I I 0 0 0 0 0 0 0 0 0 0 I I I I I I I I | Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART and the CPU. DO is the least significant bit. Chip Select: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on DO-D7 as controlled by the R/WN, RDN and Al-A4 inputs. When High, places the DO-D7 lines in the 3-State condition. Read/Write: A High input indicates a read cycle and a Low input indicates a write cycle, when a cycle is initiated by assertion of the CSN input. Address Inputs: Select the DUART internal registers and ports for read/write operations. Reset: A Low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex OF, puts OPO-OP7 in the High state, stops the counter/timer, and puts Channel A and B in the inactive state, with the TxDA and TxDB outputs in the mark (High) state. Clears Test modes, sets MR pointer to MRl. Data Transfer Acknowledge: Three-state active Low output asserted in write, read, or interrupt cycles to indicate proper transfer of data between the CPU and the DUART. Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. Interrupt Acknowledge: Active-Low input indicating an interrupt acknowledge cycle. In response, the DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending. Crystal l: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing. Crystal 2: Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected although it is permissible to ground it. Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High, "space" is Low. Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is High, "space" is Low. Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle or when operating in local loopback mode. "Mark" is High, "space" is Low. Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. 'Mark' is High, 'space' is Low. Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated automatically on receive or transmit. Output l: General purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated automatically on receive or transmit. Output 2: General purpose output, or Channel A transmitter lX or 1 6X clock output, or Channel A receiver lX clock output. Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter lX clock output, or Channel B receiver lX clock output. Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA output. Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB output. Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output. Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYB output. Input O: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal Vcc pull-up device supplying l t0 4 yA of current. Input l: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal Vcc pull-up device supplying l t0 4 yA of current. Input 2: General purpose input, or Channel B receiver external clock input (RxCB), or counter/timer external clock input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal Vcc pull-up device supplying l t0 4 yA of current. Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal Vcc pull-up device supplying l t0 4 yA of current. Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal Vcc pull-up device supplying l t0 4 yA of current. Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal Vcc pull-up device supplying l t0 4 yA of current. Power Supply: +5V supply input. Ground: |
