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TMS320C6414DCLZ7E3 Datasheet

TA=+ Pin= - 50c OdBm
Vcc =! j 5
] Vcc=! i.0 V
_ I
V e= 4 5 ·V


TMS320C6414DCLZ7E3 Price

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fmax Maximum clock frequency 30 40 MHz
tPHL Propagation delay time, high-to-low-level output from clear CL = 15 pF, 18 27 ns
tPLH Propagation delay time, low-to-high-level output from clock RL = 2 kl, See Note 3 17 27 ns
tPHL Propagation delay time, high-to-low-level output from clock 18 27 ns


TMS320C6414DCLZ7E3 on stock

Symbol Parameter Test Conditions Min Typ. Max Unit
9fs 4 Forward Transconductance VDS =15V, ID = 5.25A 12 S
Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS =25V, f=l MHz, VGS=O 2620 250 53 pF pF pF
Coss eq 5 Equivalent Ouput Capacitance VGS=O, VDS =OV t0 640V 100 pF
Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=640V, ID = 10.5 A VGS =10V (see Figure 17) 87 14 44 nC nC nC


A1 NC A2 TDI A3 NC A4 NC A5 A14L A6 AIIL A7 A8L A8 BE2L A9 CEIL A10 OEL A11 INTL A12 A5L A13 A2L A14 AOL A15 NC A16 NC
B1 l/018L B2 NC B3 TDO B4 NC B5 A15L(2 B6 A12L B7 A9L B8 BE3L B9 CEOL Bl0 R/WL B11 NC B12 A4L B13 AIL B14 NC B15 l/0i 7L B16 NC
C1 C2 C3 C4 c5 C6 C7 C8 C9 C10 Cll C12 C13 C14 C15 C16
l/018R l/019L Vss A16L(I) A13L AIOL A7L BEIL BEOL SEML BUSYL A6L A3L OPTL l/017R l/016L
D1 l/020R D2 l/019R D3 l/020L D4 VDD D5 VDDQL D6 VDDQL D7 VDDQR D8 VDDQR D9 VDDQL D10 VDDQL Dll VDDQR D12 VDDQR D13 VDD D14 11015R D15 l/OisL D16 l/016R
E1 l/021R E2 l/021 L E3 l/022L E4 VDDOL E5 VDD E6 VDD E7 Vss E8 Vss E9 Vss El0 Vss Ell VDD E12 VDD E13 VDDQR E14 11013L E15 l/014L E16 l/014R
F1 l/023L F2 l/022R F3 l/023R F4 VDDQL F5 VDD F6 Vss F7 Vss F8 Vss F9 Vss Fl0 Vss Fll Vss F12 VDD F13 VDDQR F14 l/012R F15 l/013R F16 l/012L
G1 l/024R G2 l/024L G3 l/025L G4 VDDQR G5 Vss G6 Vss G7 Vss 38 Vss G9 Vss Gl0 Vss Gll Vss 312 Vss G13 VDDQL G14 l/OlOL G15 l/0iiL G16 l/011R
H1 l/026L H2 l/025R H3 l/026R H4 VDDQR H5 Vss H6 Vss H7 Vss H8 Vss H9 Vss Hl0 Vss Hll Vss H12 Vss H13 VDDQL H14 l/09R H15 109L H16 l/OlOR
J1 l/027L J2 l/028R J3 l/027R J4 VDDQL J5 Vss J6 Vss J7 Vss J8 Vss J9 Vss Jl0 Vss Jll Vss J12 Vss J13 VDDQR J14 l/08R J15 l/07R J16 l/08L
K1 l/029R K2 l/029L K3 l/028L K4 VDDOL K5 Vss K6 Vss K7 Vss K8 Vss K9 Vss K10 Vss Kll Vss K12 Vss K13 VDDQR K14 l/06R K15 l/06L K16 l/07L
L1 l/030L L2 l/031R L3 l/030R L4 VDDOR L5 VDD L6 Vss L7 Vss L8 Vss L9 Vss Ll0 Vss L11 Vss L12 VDD L13 VDDQL L14 l/05L L15 U04R L16 l/05R
M1 l/032R M2 l/032L M3 110 31L M4 VDDQR M5 VDD M6 VDD M7 Vss M8 Vss M9 Vss Ml0 Vss M11 VDD M12 VDD M13 VDDQL M14 l/03R M15 l/03L M16 l/04L
N1 l/033L N2 l/034R N3 l/033R N4 VDD N5 VDDOF N6 VDDQR N7 VDDQL N8 VDDQL N9 VDDQR N10 VDDOR Nll VDDQL N12 VDDQL N13 VDD N14 l/02L N15 l/OIR N16 l/02R
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
l/035R l/034L TMS A16R(iI A13R AIOR A7R BEIR BEOR SEMR BUSYR A6R A3R l/OOL l/OOR 1101L
R1 l/035L R2 NC R3 TRST R4 NC R5 A15R(2) R6 A12R R7 A9R R8 BE3R R9 CEOR Rl0 R/WR R11 M/S R12 A4R R13 AIR R14 OPTR R15 NC R16 NC
T1 NC T2 TCK T3 NC T4 NC T5 A14R T6 AIIR T7 A8R T8 BE2R T9 CEIR T10 OER T11 INTR T12 A5R T13 A2R T14 AOR T15 NC T16 NC


 
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