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TMS320C6414EZLZ5E0 Datasheet

block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins l and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which turn off, allowing the SCR to reset.
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Input current	'L	8	30	¨A	VIL = 5 V; normal operation
Input current	'L	1 60	300	VA	VIL = 5 V; failure mode
Leakage current of lowside switch	IDL LK	2	1 0	¨A	VIL=OV

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		VCE=-10V
			ra=7sC
7				_
	7			_
			-2f

PARAMETER	SYMBOL	MIN	TYP.	MAX	UNIT
Address setup time	tAS	2
Chip enable setup time	tCES	2
Output enable setup time	tOES	2			Lrs
Data setup time	tDS	2
Address hold time	tAH	0
Data hold time	tDH	2			LLS
Chip enable to output float delay	tDF	0		150	ns
Data valid from output enable	tOE			150	ns
VPP setup time	tVPS	2
Vcc setup time	tvcs	2
P pulse width	tPW	0.95	1.0	1.05	ms
Add P~M pulse width	tOPW	2.85		78.75	ms
Program pulse count	N	1		25	TIMES

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