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TMS320LC31-40 Datasheet

Pin Name Description
1 VCC 5V power supply
2 VCC 5V power supply
3 VCCLNA 5V LNA power supply
4 RFIN RF input
5 GNDLNA LNA ground
6 GNDSUB Ground
7 PFD Access to VCO control voltage
8 GNDVCO VCO ground
9 GND Ground
1 0 XTAL1 Reference oscillator crystal
11 XTAL2 Reference oscillator crystal
1 2 CAGC IF AGC capacitor for OOK Reference for FSK
1 3 DMDAT Demodulated data (OOK & FSK modulation)
14 RESETB State Machine Reset
1 5 MISO SPI interface I/O
1 6 MOSI SPI interface l/0
1 7 SCLK SPI interface clock
1 8 VCCDIG 5V digital power supply
1 9 GNDDIG Digital ground
20 RCBGAP Reference voltage output
21 STROBE Strobe oscillator control Stop/Run external control input
22 CAFC AFC capacitor
23 MIXOUT Mixer output
24 CMIXAGC Mixer AGC capacitor


TMS320LC31-40 Price

VD5=VcS
ID_250, A
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TMS320LC31-40 on stock
The TAS3002 device supports 13 serial interface formats (12S, left justified, right justified) with data word lengths of 16, 18, 20, or 24 bits. The sampling frequency (fS) may be set t0 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface formats are listed and described in Section 2.1.

Parameter Symbol Conditions Min Typ Max U nits
High Side Driver
rise time trTG1 CI = 3riF, VBST - VDRN = 4.6V, 14 23 ns
fall time tfTG CI = 3riF, VBST - VDRN = 4.6V, 12 19 ns
propagation delay time, TG going high tpd hTG CI = 3riF, VBST - VDRN = 4.6V, C-delay=0 20 32 ns
propagation delay time, TG going low tpdITG CI = 3riF, VBST - VDRN = 4.6V, 1 5 24 ns
Low-Side Driver
rise time trBG CI = 3nF, V v s = 4.6V, 1 5 24 ns
fall time trBG CI = 3nF, V v s = 4.6V, 1 3 21 ns
propagation delay time, BG going high tpdhBGH, CI = 3riF, VBST - VDRN = 4.6V, C-delay=0 12 19 ns
propagation delay time, TG going low tpdIBG CI= 3nF, V y s = 4.6V, DRN <1V 7 12 ns
Under-Voltage Lockout
V-5 ramping up tpdhUVLO EN is High 10 us
V-5 ramping down tpdhUVLO EN is High 10 us
PRDY
EN is transitioning from low to high tpdhPRDY V-5 >UVLO threshold, Delay measured from EN > 2.OV to PRDY> 3.5V 10 LJs
EN is transitioning fro high to low tpdhUVLO V-5 >UVLO threshold, Delay measured from EN < 0.8V to PRDY< 10% ofV 5V 500 LJs
DSPS DR
rise/fall time trDSPS DR CI = 100 pf, V-5 = 4.6V 20 ns
propagation delay, DSPS_DR going high tpdhDSPS DR S_MOD goes high and BG goes high or S_MOD goes low 10 ns
propagation delay, DSPS~DR goes low tpdIDSPS DR S_MOD goes high and BG goes low 10 ns
Overvoltage Protection
propagation delay tpdhOVP s V-5 + 4.6V, TJ = 1250C, OVP S > 1.2V to BG > 90% ofV 5 1 LJs