TIMap-3  > TMS32OC51PZ80

suppliers of TMS32OC51PZ80 and PDF data of TMS32OC51PZ80

Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  

TMS32OC51PZ80 Datasheet
The USB l.1 full-speed host controller allows the playback device to connect directly to digital cameras and either display images from the DSC or download them to the playback device. The USB l.1 full-speed slave controller can be used to connect to a PC for downloading of images from the playback device to the PC. The USB 2.0 high-speed slave controller can also be used to connect to a PC for the downloading of images from the playback device to the PC. This interface is mutually exclusive from the USB l.1 interfaces (see "Part Versions" below). An USART interface is included for serial communication. It supports standard baud rates of up t0 460.8 Kbps or non-standard rates of up t0 4.875 Mbps in asynchronous mode. It supports rates of up t019.5 Mbps in synchronous mode. The serial peripheral interface (SPI) is used to boot from an external EEPROM. Once the boot code is loaded inside the program memory, the CPU can download its code from any peripheral supported by the device, including non-volatile storage media. With two chip select pins, the SPI can also be used to control other external devices at speeds of up t0 19.2 Mbps with 64-bit transfers. Throughput decreases if the transfer size is reduced or the delay between transfers is increased. Three 16-bit general-purpose timers are included and can be used to generate interrupts to the internal CPU. They can generate waveforms on their associated pins via Pulse-width Modulation (PWM) or other techniques. They can also monitor and count external events on these pins.
TMS32OC51PZ80 Price

I -
r
j
i
= t5ao 7 |
J J oc
|
l J
l f VGS - ov


TMS32OC51PZ80 on stock
Expansion Logic is used when implementing a FIFO of a depth greatar than that of the 67C4502. The write, read, data-in and data-out lines of the 67C4502 are connectedin parallel, and the Expansion-Out (XO) and the Expansion-In (XI) lines are daisy- chained together. The write and read control circuits of the individ- ual FIFOs are automalcally enabled and disabled through the handshake between XO and XI.
c o L n 4 3 2 r O O ) C 0 7 ( O L 0 4 3 2 r 0 9 8 7 6 L f ) 4 c v ) 2 r 0 9 5 5 5 5 L r , L O L O . t - : t : t . t - : t t . t - : t t . t ( t , ( t , ( t , ( v , ( t , ( f , ( t , ( Y ) C f ) ( t , 2