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duce a logic state and in the other direction to produce the other logic state. The output current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as discussed above) that a resistive termi- nation be employed to terminate the signal and to complete the loop as shown in Figure 6. AC or unterminated configu- rations are not allowed. The 3.5 mA loop current will develop a differential voltage of 350 mV across the 100 I termination resistor which the receiver detects with a 250 mV minimum dierential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV - 100 mV = 250 mV. The signal is centered around +1.2V (Driver Off- set, Vos) with respect to ground as shown in Figure 7. Note that the steady-state voltage (Vss) peak-to-peak swing is twice the differential voltage (Voo) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quies- cent current remains relatively flat versus switching fre- quency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz-50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the cur- rent mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static lcc requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifica- tions for the driver are a tenfold improvement over other ex- isting RS-422 drivers.
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