| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
TMS70C42 Datasheet
TMS70C42 Price The requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during Vcc power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array. TMS70C42 on stock The fastest instruction at 20 MHz frequency 50 ns ~ Interrupts ........... 8 external sources, 23 internal sources, 7 levels ~ Multi-functional 1 6-bit timer ....... ............... 10 + 3 (Three-phase motor drive waveform or Pulse motor drive waveform output is available.) ~ Serial l/0 (UART or Clock synchronous) 3 ~ 1 0-bit A-D converter ................... ............. 12-channel inputs ~ 8-bit D-A converter .... .............2-channel outputs ~ 12-bit watchdog timer ~ Programmable inpuVoutput (ports Pl, P2, P4, P5, P6, P7, P8) 50 This circuit provides a programmable (by external capaci- tor) delay on the RESET output lead. The Delay lead pro- vides source current to the external delay capacitor only when the Low Voltage Inhibit circuit indicates that output voltage is above VRTH. Otherwise, the Delay lead sinks current to ground (used to discharge the Delay capacitor). The discharge current is latched ON when the output volt- age falls below VRrL. The Delay capacitor is fully dis- charged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a con- trolled RESET pulse is generated following the detection of an error condition. The circuit allows the RESET out- |
