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TMX320C25FNLR Datasheet

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		\|\|		nBl
	~	tstg		Vinl50D
		fI		vaBL'''zL . vcc=JU v
				IC=10'IB1
7 1			t	= - iu'182 PW<2 pS duty cycleS2 % I I I I ill I I I I I l III I I
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TMX320C25FNLR Price

SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: - All features specified for Layer lIl in ISO/IEC 11172-3 (MPEG l Audio) - All features specified for Layer lIl in ISO/IEC 13818-3.2 (MPEG 2 Audio) - Lower sampling frequencies syntax extension (not specified by ISO) called MPEG 2.5
TMX320C25FNLR on stock

PARAMETER	SYMBOL	MIN	MAX	UNIT	CONDITIONS
Turn-On Time	ton		35	ns	Vcc-30V, VBE(oft)=2V lc=150mA, IBl=15mA (See Fig.l)
Turn-Off Time	toff		255	ns	Vcc-30V, lc-150mA IBl=IBr15mA (See Fig. 2)

Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, while Status Register data out- puts on DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C. operations. A Ready/Busy (RB) output indicates the completion of the internal algorithms.

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