| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| TMX320LC56PZ80 | TEXASINSTRUM | N/A | 105 |
|
|
TMX320LC56PZ80 Datasheet To drive the device from an external clock source, XTALl should be driven, while XTAL2 floats, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal, since the in- put to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. TMX320LC56PZ80 Price DESCRIPTION: The IDT72V275/72V285 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs,includingthefollowing: .. The limitation ofthe frequency ofone clockinputwith respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which ofthe two clock inputs, RCLK or WCLK, is running at the higher frequency. .. The period required by the retransmit operation is now fixed and short. .. The first word data latency period,from the time the firstword is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyncfamily.) S uperSync FIFOs are pa rticula rly appro p riate fo r network, video, telecom- m unications, data com munications and other applications that need to buffer largeamountsofdata. TMX320LC56PZ80 on stock When using the CXG1008N, the following external components should be used: Ci: This is used for signal line filtering. 100 pF is recommended. C2: This is used for RF De-coupling and must be used in all applications. 100 pF is recommended. Di: 6.2 V Zener diodes may be incorporated at the Control lines, as indicated, in order to give improved ESD performance if necessary.
|
