| INPUT | OUTPUT | |
| SH CP | ST CP | OE | MR | DS | Q7' | Qn | FUNCTION |
| x | x | L | L | x | L | nC | a LOW level on MR only affects the shift registers |
| x | | L | L | x | L | L | empty shift register loaded into storage register |
| x | x | H | L | x | L | Z | shift register clear; parallel outputs in high-impedance OFF-state |
| | x | L | H | H | Q6' | nC | logic high level shifted into shifl register stage 0; contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6') appears on the serial output (Q7') |
| x | | L | H | x | nC | Qn' | contents of shift register stages (internal Qn') are transferred to the storage register and parallel output stages |
| | | L | H | x | Q6' | Qn' | contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages |
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