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suppliers of TN2425N8-G and PDF data of TN2425N8-G

Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
TN2425N8-G	SUPERTEX	SOT-89	09+	STOCK	1000	HXD Electronics Co. Contact:betty Tel:00852-95611784 Fax:00852-95611893 Email: betty@hxdic.net
TN2425N8-G	SUPERTEX	SOT-89	06+		134	Akebi(HK)Eletronics Co.,LTD Contact:spark Tel:86-755-88357655 Fax: Email: akebi520@gmail.com
TN2425N8-G			08+	SUPERTEX	2354	Sinco International Company Contact:Tina Tel:86-10-82638179 Fax: Email: tina.zhao.sinco@gmail.com
TN2425N8-G		EXCESS	08+		2354	Shenzhen Chitron Electronics C.. Contact:yao Tel:86-755-82116111 Fax: Email: stocksales@chitron.com
TN2425N8-G	Supertex	SOT-89	06+		15000	Highlight Electronics (H.K) Co.. Contact:Ava Tel:86-755-8375-9556 Fax:86-755 83759277 Email: sales3@highlight-ic.com
TN2425N8-G	SUPERTEX		07+		5600	HK CHISHING ELECTRONICS CO., Contact:maggielee Tel:86-755-61303995 Fax:86-755-61306028 Email: maggielee@zcicgs.com.cn
TN2425N8-G	SUPERTEX	SOT89	06+		2000	HONGFAXINELECTRONIC(ASIA)LIMIT.. Contact:Mr.Chen Tel:086-0755-82736393 Fax:086-0755-83987202 Email: tony@hfxelec-asia.com

TN2425N8-G Datasheet

Reverse Recovery Time trr IFM = 200A, Tj = 1501C 0.2 0cs di/dt = -1000A/s, VR = 300V
TN2425N8-G Price

nformation, contact your Agere Systems Account Manager or the following: http://www.agere.com docmaster@agere.com Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) Tel. (44) 7000 624624, FAX (44) 1344 488 045
TN2425N8-G on stock

I/O Bus. The 287010 provides a 16-bit, CMOS compatible I/O bus. I/0 Control pins provide convenient communica- tion capabilities with external peripherals. Single cycle ac- cess is possible. For slower communications, an on-board hardware wait-state generator can be used to accommo- date timing conflicts.

In the execution cycle, the fetched instruction is latched into the "Instruction Register (IR)" in cycle Ql. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

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