| Control | Default | 0 | 1 |
| VCO SEL | 0 | VCO | VCO X/2 |
| PLL EN# | 0 | PLL enabled. The VCO output connects to the output dividers | Bypass mode, PLL disabled. The input clock connects to the output dividers |
| MR/OE# | 0 | Outputs enabled | Outputs disabled (three-state), VCO running at its minimum frequency |
| SELA | 0 | QA= VCO4 | QA= VCO6 |
| SELB | 0 | QB =VCO x/4 | QB= VCO2 |
| SELC | 0 | QC= VCO x/2 | QC= VCO x/4 |
| | | |
At the end of each serial register, there is an output summing well which can be clocked to allow multiple-pixel summation of the scene. This summing well is located after the 49th extra stage of the horizontal registers and prior to the D(: biased gate
