suppliers of TN30X010NL2 and PDF data of TN30X010NL2

A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the Sl line followed by the byte address and the data (D7-DO) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The LOW to High transition of the CS pin must occur during the SCK low time immediately after clocking in the DO (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruc- tion. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE pro- gramming cycle. The AT25P1024 is capable of a 128-byte PAGE WRITE operation ONLY. Content of the page in the array will not be guaranteed if less than 128 bytes of data is received (byte operation is not supported). After each byte of data is received, the seven low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 128 bytes of data are trans- mitted, the address counter will roll over and the previously written data will be overwritten. The AT25P1024 is auto- matically returned to the write disable state at the comple- tion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication.