TN80C188EA2 Datasheet| jL | | 170HFL. Series R+v i,_ (DC) = 0.53 K/W | | | | | k | | | l | | | | j | | | | 4 | | | | | 1 | | | | tio n | ngle | | | | j | | | j | | | | | | | 1 | | | ) | ) | | | | | | 300 | -61 | | 91 | )0 | l 200 | | | | | | | | | | | 11810 | | | | | | | | | | |
TN80C188EA2 Price Power Supply. The device power supply, 13.5 V nominal for automotive applications, is connected to the battery through an external diode, in order to protect against reversal ofbattery polarity. To comply with the LIN Bus protocol, there must be no more than a l V drop between the battery potential and the supply pin. The A8423 0perates continu- ously up t0 30 V, and withstands 40 V during a 500 ms load dump. Ifthe supply drops below the undervoltage limit, this condition is detected and the A8423 disables the transmission path and the 5 V regulator, while maintaining a high-imped- ance state on the LIN terminal. TN80C188EA2 on stock| | | | | | | l l l Tc= 250C | | | | | | | | F | 'uISf | } Tei | | | | | l | | | | | | | | | | | | | | | | 1 l ID= 25A | | | | | | | | | | | | | | | | '- | | | | | 20A | | | | | | | | | | | | | | | | ~ | | | | | 14A | | | | | | | | | | 7A | | | | | | | | | | | | | | | | | | | | | |
| BAi | BAo | Aii | Aio | A9 | A8 | A7 | A6 | As | A4 | A3 | A2 | Ai | Ao | Address Bu | | l, 1, 1, 1 1, 1, 1, 1, 1 1, 1 1 1, 1, | | RFU | 0 | RFU | DLL | TM | CAS Latency | BT | Burst Length | Mode Regis | | | l TestMod l | L | rl | | | DLL Te | I Burst Type | | | | A8 | DLL Reset | | A7 | mode | | A3 | Type | | | 0 | No | 0 | Normal | 0 | Sequential | | 1 | Yes | 1 | Test | 1 | Interleave | | | Burst Length | | CAS Latency | | A2 | Ai | Ao | Burst Type | | BAo | AnAo | | A6 | As | A4 | Latency | | Sequential | Interleave | | 0 | MRS | 0 | 0 | 0 | Reserved | 0 | 0 | 0 | Reserve | Reserve | | 1 | EMRS | 0 | 0 | 1 | Reserved | 0 | 0 | 1 | 2 | 2 | | | 0 | 1 | 0 | Reserved | 0 | 1 | 0 | 4 | 4 | | 0 | 1 | 1 | 3 | 0 | 1 | 1 | 8 | 8 | | * RFU(Reserved for future use) | 1 | 0 | 0 | Reserved | 1 | 0 | 0 | Reserve | Reserve | | should stay "0" during MRS cycle. | 1 | 0 | 1 | Reserved | 1 | 0 | 1 | Reserve | Reserve | | 1 | 1 | 0 | Reserved | 1 | 1 | 0 | Reserve | Reserve | | 1 | 1 | 1 | Reserved | 1 | 1 | 1 | Reserve | Reserve | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
