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TND311 Datasheet

CHARACTERISTIC	SYMBOL	RATING	UNIT
Collector-Base Voltage	VCBO	40	v
Collector-Emitter Voltage	VCEO	15	v
Emitter-Base Voltage	VEBO	5	V
Collector Current	IC	200	mA
Base Current	IB	40	mA
Collector Power Dissipation	PC	100	mW
Junction Temperature	Tj	125	oC
Storage Temperature Range	Tstg	- 55125	oC

TND311 Price

General Description The MIC2224 is a high eiciency 2MHz PWM synchronous buck switching regulator optimized for powering 2.5G and 3G CDMA RF Power Amplifiers. The output voltage of MIC2224 can be dynamically adjusted with an external DAC to maximize PA efficiency versus required output power. When the PA requires the highest power, the DAC can be used to enable a low on-resistance, 40mQ, bypass switch that powers the PA directly from the battery.
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VCE = -10 V					-
T. = 25'C
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Pin No.		Symbol	Description
LQFP (X18)	LQFP (X36)	Symbol	Description
37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 83 84 80	37 36 35, 34, 33, 32, 100, 99, 82, 81, 45, 46, 47, 48, 49, 50, 83, 84 44	AO A1 A2 - A9 A11 - A18 A19 A10	Synchronous Address Inputs : These inputs are registered and must meet the setup and hold times around the rising edge of CLK. AO and Al are the two lest significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
93 (BW ) 94 (BW2)	93 (BW ) 94 (BW2) 95 (BW3) 96 (BW4)	BW1 BW2 BW3 BW4	Synchronous Byte Write Enables : These active low inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address, BWs are associated with addresses and apply to subsequent data. BWl controls l/Oa pins; BW2 controls l/Ob pins; BW3 controls l/Oc pins; BW4 controls l/Od pins.
89	89	CLK	Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock are rising edge.
98	98	CE	Synchronous Chip Enable : This active low input is used to enable the device. This input is sampled only when a new external address is loaded (ADV/LD LOW).
92	92	CE2	Synchronous Chip Enable : This active low input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD LOW). This input can be used for memory depth expansion.
97	97	CE2	Synchronous Chip Enable : This active high input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD LOW). This input can be used for memory depth expansion.
86	86	OE	Output Enable : This active low asynchronous input enables the data l/0 0utput drivers.
85	85	ADV/LD	Synchronous Address Advance/Load : When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, R/W is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge.
87	87	CEN	Synchronous Clock Enable : This active low input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK.

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