| PIN | | |
| DIP, SO | MODULE | TSOP | NAME | FUNCTION |
| 1 | 1 | 8 | PWR | Active-Low Power-On Output (Open Drain). This output, if used, is normally connected to power-supply control circuitry. This pin requires a pullup resistor connected to a positive supply to operate correctly. |
| 2.3 | | 9. 10 | X1X2 | Connections for Standard 32.768kHz Quartz Crystal. For greatest accuracy, the DS1501 must be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal select (CS) bit in control register B is used to select operation with a 6pF or 12.5pF crystal. The crystal is attached directly to the Xl and X2 pins. There is no need for external capacitors or resistors. An external 32.768kHz oscillator can also drive the DS1501. In this configuration, the Xl pin is connected to the external oscillator signal and the X2 pin is floated. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. See Figure 9. An enable bit in the month register controls the oscillator. Oscillator startup time is highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within one second. |
| 4 | 4 | 11 | RST | Active-Low Reset Output. (Open Drain). This output, if used, is normally connected to a microprocessor-reset input. This pin requires a pull up resistor connected to a positive supply to operate correctly. When RST is active, the device is not accessible. |
| 5 | 5 | 12 | IRCl | Active-Low Interrupt Output (Open Drain). This output, if used, is normally connected to a microprocessor interrupt input. This pin requires a pullup resistor connected to a positive supply to operate correctly. |
| 6-10 | 6-10 | 13-17 | A4-AO | Address Inputs. Selects one of 17 register locations. |
| 11-13, 15-19 | 11-13, 15-19 | 18-20, 22-26 | DQO-DQ7 | Data Input/Output. I/0 pins for 8-bit parallel data transfer. |
| 14, 21 | 14 | 21, 28 | GND | Ground. DC power is applied to the device on these pins. Vcc is the positive terminal. When power is applied within the normal limits, the device is fully accessible and data can be written and read. When Vcc drops below the normal limits, reads and writes are inhibited. As Vcc drops below the battery voltage, the RAM and timekeeping circuits are switched over to the battery. |
| 22 | 22 | 1 | OE | Output-Enable Input. Active-Iow input that enables DQO-DQ7 for data output from the device. |
| 20 | 20 | 27 | CE | Chip-Enable Input. Active-Iow input to enable the device. |
| 23 | 23 | 2 | SQw | Square-Wave Output. When enabled, the SQW pin outputs a 32.768kHz square wave. If the square wave (E32K) and battery backup 32kHz (BB32) bits are enabled, power is provided by VBAUX when Vcc is absent. |
| 24 | 24 | 3 | KS | Active-Low Kickstart Input. This pin is used to wake up a system from an external event, such as a key closure. The KS pin is normally connected using a pullup resistor to VBAUX. If the KS function is not used, connect to ground. |
| 25 | | 4 | VBAT | Battery Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. If not used, connect to ground.' |
| 26 | 26 | 5 | VBAUX | Auxiliary Battery Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. If not used, connect to ground.' |
| 27 | 27 | 6 | WE | Write-Enable Input. Active-Iow input that enables DQO-DQ7 for data input to the device. |
| 28 | 28 | 7 | Vcc | DC Power. Vcc is the positive terminal. When power is applied within the normal limits, the device is fully accessible and data can be written and read. When Vcc drops below the normal limits, reads and writes are inhibited. As Vcc drops below the battery voltage, the RAM and timekeeping circuits are switched over to the battery. |
| | 2,3,21 25 | | NC | No Connect |
| | | | |
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assu res that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
TNPW-0805-4991-D-T-9 on stock SHDN (Pin 4): Shutdown Pin. This pin is used to put the device into shutdown. In shutdown the output of the device is turned off. This pin is active low. The device will be shut down if the SHDN pin is actively pulled low. The SHDN pin currentwith the pin pulled to ground will be 6 The SHDN pin is internally clamped t0 7V and -0.6V (one VBE). This allows the SHDN pin to be driven directly by 5V logic or by open-collectorlogic with a pull-up resistor. The pull-up resistor is only required to supply the leakage current of the open-collector gate, normally several mi- croamperes. Pull-up current must be limited to a maxi- mum of 5mA. A curve of SHDN pin input current as a
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge ofCE or WE. Each byte pair to be programmed must have its high-to-low transition on WE (or CE) within 150 ccS of the low-to- high transition ofWE (or CE) of the preceding byte pair. If a high-to-low transition is not de- tected within 150 ccS of the last low-to-high transition, the data load period will end and the intemal programming period will start. All the bytes of a sector are simultaneously programmed during the intemal programming period. A maximum write time of 10 ms per sector is self-controlled by the Flash devices. Refer to A.C. Write Waveforms drawmgs.
