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TNPW0805-8871BT9 Datasheet

Parameter	Symbol	Condition	Min.	Typ.	Max.	Unit
		VDD=3V	1000			ns
Enable Cycle Time	tcycE	VDD=5V	500			ns
		VDD=3V	450			ns
Enable Pulse Width (High Level)	PWEH	VDD=5V	230			ns
		VDD=3V			25	ns
Enable Rise/ Fall Time	tEf, tEr	VDD=5V			20	ns
		VDD=3V	60			ns
Address Set-up Time (RS, R/WB to E)	tAS	VDD=5V	40			ns
		VDD=3V	20			ns
Address Hold Time	tAH	VDD=5V	10			ns
		VDD=3V			360	ns
Data Delay Time	tDDR	VDD=5V			160	ns
		VDD=3V	5			ns
Data Hold Time	tDHR	VDD=5V	5			ns

TNPW0805-8871BT9 Price

PC board layout is important to insure that leakage cur- rents do not corrupt the low IBIAS of the amplifier. In high precision, high impedance circuits, the input pins should be surrounded by a guard ring of PC board interconnect, with the guard driven to the same common mode voltage as the amplifier inputs.
TNPW0805-8871BT9 on stock

NOTES: A. CLlncludes probe and jig capacitanca. B. Input pulses are supplied by generators having tha following charactaristics: PRR s 10 MHz. ZO = 50 fZ, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a tima with one Input transitian per measurement. FIgure l. Load CircuIt and Voltage Waveforms

=5v

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25 0C

-40G

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