TNPW120610002BTATR Datasheet When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (DO) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. TNPW120610002BTATR Price (1) WE is High for Read Cycle. (2) All read cycle timing is referenced from the last valid address to the first transition address. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for agiven module and from module to module. TNPW120610002BTATR on stock| Pre-Radiation Electrical Specifications Tc = +250C, Unless Otherwise Specified | | | | | | LIMITS | | | | PARAMETER | SYMBOL | TEST CONDITIONS | MIN | MAX | UNITS | | Drain-Source Breakdown Volts | BVDSS | VGS = O, ID = ImA | 100 | | V | | Gate-Threshold Volts | VGS(th) | VDS = VGS,ID = 1mA | 2.0 | 4.0 | V | | Gate-Body Leakage Forward | IGSSF | VGS= +20V | | 100 | nA | | Gate-Body Leakage Reverse | IGSSR | VGS - -20V | | 100 | nA | | Zero-Gate Voltaga Drain Current | IDSS1 IDSS2 IDSS3 | VDS = 100V, VGS = o VDS = 80V, VGS = o VDS = 80V, VGS = 0, TC = +1250C | | 1 0.025 0.25 | mA | | Rated Avalancha Current | IAR | Time= 20p.s | | 51 | A | | Drain-Source On-Stata Volts | VDS(on) | VGS = 10V,ID = 17A | | 2.59 | V | | Drain-Source On Resistance | RDS(on) | VGS = 10V,ID = 11A | | O145 | Q | | Turn-On Delay Time | td(on) | VDD = 50V,ID = 17A | | 60 | | | Rise Time | | Pulse Width = 3Vs | | 320 | ns | | Tum-Off Delay Time | td(off) | Period = 300ys, RG = 2501 | | 290 | | Fall Tlnw | tr | o < VGS < 10 (See Test Circuit) | | 260 | | Gate-Charge Threshold | QG(W | | 1 | 6 | | | Gata-Charge On State | QG(on) | 32 | 130 | nc | | Gate-Charge Total | QGM | VDD - 50V,ID = 17A IGSl = IGS2 | 60 | 240 | | Plateau Voltage | VGP | o s VGS120 | 3 | 14 | V | | Gate-Charge Source | QGS | 5 | 22 | nc | | Gate-Charge Drain | QGD | 18 | 74 | | Diode Forward Voltage | VSD | ID = 17A, VGD = o | O6 | 1.8 | V | | Reversa Recovery Time | TT | 1:17A; dr7dt = lOONys | | 800 | ns | | Junction-To-Case | ROjc | | | 1.67 | oc/W | | Junction-To-Ambient | ROja | Free Air Operation | | 60 | | E1 ~ 0.5 BVDSS = 0.75 BVDSS ' FIGURE l. SWITCHING TIME TESTING FIGURE 2. CLAMPED INDUCTIVE SWITCHING,ILM | | | | | | | | |
| tCLK tWH | 1200 600 | 300 | 600 CLK L Pulse Width | tWL | | CLK H Pulse Width | | | | | | | | | | | | | | | 30050Eetupimecs? | 400 | 200 | CE hold time | tCH | | | CE recovery time | tCR | 600 | | 300 | | | CLK hold time | tCKH | | ns | | | Write data setup time | tDS | 100 Write data hold time | | 50 tDH | | | | | | | | | | | Read0data delay time Read data disable delay time | 200 200 | 0 | 100 | 400 | | | 40 | 20 | | | Rise and fall time | tRF | | | 40 | 60 | FOUT duty ratio (32.768KHz output) | % Duty | 35 | 65 | | | | | | | | | | | | | | | | | | | | |
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