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Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the reg- ister is greater than the byte on the data bus, the EQ and LT outputs will be pulled LOW and the GT output will float HIGH. Also the C/SO output of the most significant device will be forced LOW, disabling the subsequent devices but enabling its own status outputs. The correct status condition is thus indicated. The same applies if the registered byte is less than the data byte, only in this case the ECl and GT outputs go LOW and LT output floats HIGH. If an equality condition is detected in the most significant device, its C/SO output is forced HIGH. This enables the next less significant device and also disables its own status outputs. In this way, the status output priority is handed down to the next less significant device which now effec- tively becomes the most significant byte. The worst case propagation delay for a compare operation involving 'n' cas caded 'F524s will be when an equality condition is detected in all but lhe least significant byte. Jn this case, the status priority has to ripple all the way down the chain before the correct status output is established. Typically, this will take 35 + 6(n-2) ns.
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