The basic pad layout with dimensions is shown in Figure 18. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 19 improves the thermal area of the drain connections (pins 5, 6) while remaining within the confines
| 1 7r | N | P | Q |
| lhFE | 56120 | 82180 | 120270 |
| | | |
Fourteen fully prioritized vectored interrupts-10 external, 2 internal, 2 software Specialized DSP integer Multiply- Accumulate instructions (MAD/MADU), and three-operand Multiply instruction (MUL) I and D Test/Break-point (Watch) registers for emulation and debug Performance counter for system and software tuning and debug
