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Once the write enable latch is set, the user may pro- ceed by setting the CS low, issuing a write instruction, followed by the 16-bit address, with the four MSBs of the address being don't care bits, and then the data to be written. Up t0 32 bytes of data can be sent to the 25C320 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with XXXX XXXX XXX0 0000 and ends with XXXX XXXX XXX1 1111. If the internal address counter reaches XXXX XXXX XXX1 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS must be brought high after the least significant bit (DO) of the ntr' data byte has been clocked in.lf CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-3 and Figure 3-4 for more detailed illustrations on the byte write sequence and the page write sequence respectively.