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GENERAL DESCRIPTION The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,1 0 8,8 64 bit s organized in a x16 con figuration. Th e MT4 LC 4 Ml 6F5 is fu n ction ally organized as 4,194,3 04 locations containing 16 bits each. The 4,194,304 m em ory lo cation s are arran ged in 4,0 9 6 rows by l,024 colu m n s. D u rin g READ or W RITE cycle s, each lo catio n is uniquely addressed via the address bits: 12 row- address bits (AO-A11) an d 10 column -address bit s (AO- A9). In addition, both byte and word accesses are supported via th e two CAS# pin s (CASL# an d CASH#). Th e CAS# functionality and timin g related to address an d con trol fu n ction s (e.g., latch in g colu m n addre sses or selecting CBR REFRESH) are such that the internal